AI Hardware Summit Europe | Kisaco Research

The ecosystem event for AI hardware acceleration in Europe

View 2019 US Agenda
Munich, Germany
10-11 March, 2020

“I think this conference is turning out to be great in the sense that the density of companies attending it is phenomenal. All of the top notch companies are here, not fully disclosing what they’re doing but at least you get their philosophy and you get some insight from the CEOs and CTOs.”

Marc Tremblay, Distinguished Engineer, Microsoft

Why Attend

After three successful events (two in the US, one in China) we’re delighted to be bringing the AI Hardware Summit to Munich. We’ve been honoured with previous keynote speakers such as Dr. John L. Hennessey, Chairman of Alphabet, Lip-Bu Tan, CEO of Cadence Systems and Naveen Rao, CVP & GM of Intel’s AIPG.

Europe is struggling to keep up with developments in machine learning at the same pace as the US and China, where many of the top labs are located and investments are significantly larger. Due to its academic strength in AI, the potential for Europe to catch up in AI research is massive and could add enormous value to its combined economic output. Institutes like the ELLIS Society are working closely with top European academics to enable Europe to perform the best fundamental AI research, but there is still a large gap in GDP investment when compared to the US and China. 

Given Europe’s strength in automation across industrial, robotics and autonomous vehicles manufacturing, this summit will focus on inference systems in edge computing, connecting these industries through common challenges in systems architecture/engineering. The AI Hardware Summit Europe will bring together key players across the AI hardware ecosystem to promote innovation and adoption of systems & silicon for processing AI.

1000
Attendees across portfolio
100+
Leading speakers across portfolio
3
Industry Leading Summits

Speakers

 

Oliver Temam

Hardware Engineer
DeepMind

Oliver Temam

Hardware Engineer
DeepMind

Oliver Temam

Hardware Engineer
DeepMind
 

Cyra Richardson

General Manager
Microsoft

Cyra Richardson is the General Manager for Microsoft’s cross company initiative on Robotics – including both IoT and AI. Since 1990, she has played a role in many of Microsoft’s technology transformations. As an engineer Richardson helped to develop Windows 3.0 and Windows CE, as well as created developer tools for Windows CE and bringing Visual Basic to market. Richardson also launch and build several key Microsoft projects including Windows Imaging, thin versions of Windows Server, Azure Intelligent System Service and Windows 10 IoT.

Cyra Richardson

General Manager
Microsoft

Cyra Richardson

General Manager
Microsoft

Cyra Richardson is the General Manager for Microsoft’s cross company initiative on Robotics – including both IoT and AI. Since 1990, she has played a role in many of Microsoft’s technology transformations. As an engineer Richardson helped to develop Windows 3.0 and Windows CE, as well as created developer tools for Windows CE and bringing Visual Basic to market. Richardson also launch and build several key Microsoft projects including Windows Imaging, thin versions of Windows Server, Azure Intelligent System Service and Windows 10 IoT. She has also built and operated Microsoft developer programs including Platinum Hosting and the IoT & AI Insider Program.

 

Uri Weiser

Professor Emeritus
Technion

Uri Weiser is a emeritus professor at the Electrical Engineering department of the Technion IIT. He is also active on the advisory boards of numerous startups.He earned his Ph.D in CS from the University of Utah, Salt Lake City.

Uri Weiser

Professor Emeritus
Technion

Uri Weiser

Professor Emeritus
Technion

Uri Weiser is a emeritus professor at the Electrical Engineering department of the Technion IIT. He is also active on the advisory boards of numerous startups.He earned his Ph.D in CS from the University of Utah, Salt Lake City.
Uri worked at Intel from
 1988-2006 where he initiated and drove the definition of the first Pentium® processor, led the Intel’s MMX™ technology, co-invented the Trace Cache, co-managed Intel’s new Design Center at Austin, Texas and formed an advanced media applications research activity. Uri was appointed Intel Fellow; he is an ACM Fellow, and Fellow of the IEEE.
Prior to his career at Intel, Uri Weiser worked at the Israeli Department of Defense and later with National Semiconductor Design Center in Israel, where he led the design of the NS32532 microprocessor.

 

Michaela Blott

Distinguished Engineer
Xilinx

Michaela Blott is a Distinguished Engineer at Xilinx Research in Dublin, Ireland, where she heads a team of international scientists driving exciting research to define new application domains for Xilinx devices, such as machine learning, in both embedded and hyperscale deployments. She earned her Master’s degree from the University of Kaiserslautern in Germany and has over 25 years of experience in leading edge computer architecture and advanced FPGA and board design, in research institutions (ETH Zurich and Bell Labs) and development organizations.

Michaela Blott

Distinguished Engineer
Xilinx

Michaela Blott

Distinguished Engineer
Xilinx

Michaela Blott is a Distinguished Engineer at Xilinx Research in Dublin, Ireland, where she heads a team of international scientists driving exciting research to define new application domains for Xilinx devices, such as machine learning, in both embedded and hyperscale deployments. She earned her Master’s degree from the University of Kaiserslautern in Germany and has over 25 years of experience in leading edge computer architecture and advanced FPGA and board design, in research institutions (ETH Zurich and Bell Labs) and development organizations. She is heavily involved with the international research community serving as the technical co-chair of FPL’2018, workshop organizer (H2RC), industry advisor on numerous EU projects, member of numerous technical program committees (FPL, ISFPGA, DATE, etc.) and winner of the WMB award in 2015 and finalist of VentureBeat Women in AI’2019, and Women in Technology‘2019 awards.

 

Luca Benini

Full Professor of Digital Circuits and Systems
ETH Zurich

Luca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Universita di Bologna. He received a PhD from Stanford University. He has been visiting professor at Stanford University, IMEC, EPFL. In 2009-2012 he served as chief architect in STmicroelectronics France. Dr. Benini's research interests are in energy-efficient computing systems design, from embedded to high-performance. He is also active in the design ultra-low power VLSI Circuits and smart sensing micro-systems.

Luca Benini

Full Professor of Digital Circuits and Systems
ETH Zurich

Luca Benini

Full Professor of Digital Circuits and Systems
ETH Zurich

Luca Benini holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Universita di Bologna. He received a PhD from Stanford University. He has been visiting professor at Stanford University, IMEC, EPFL. In 2009-2012 he served as chief architect in STmicroelectronics France. Dr. Benini's research interests are in energy-efficient computing systems design, from embedded to high-performance. He is also active in the design ultra-low power VLSI Circuits and smart sensing micro-systems. He has published more than 900 peer-reviewed papers and five books. He is an ERC-advanced grant winner, a Fellow of the IEEE, of the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award.

 

Victoria Rege

Director of Alliances & Strategic Partnerships
Graphcore

Victoria has over a decade of experience in the semiconductor space. She currently heads up Strategic Partnerships at Graphcore, working with key customers and leading Research & Universities AI engagements. Previously she held several leadership positions at NVIDIA from global alliances, product marketing and campaigns to the founding of the GPU Technology Conference. Prior to joining NVIDIA, Victoria worked in the hedge fund space, as Executive Director for the Hedge Fund Business Operations Association.

Victoria Rege

Director of Alliances & Strategic Partnerships
Graphcore

Victoria Rege

Director of Alliances & Strategic Partnerships
Graphcore

Victoria has over a decade of experience in the semiconductor space. She currently heads up Strategic Partnerships at Graphcore, working with key customers and leading Research & Universities AI engagements. Previously she held several leadership positions at NVIDIA from global alliances, product marketing and campaigns to the founding of the GPU Technology Conference. Prior to joining NVIDIA, Victoria worked in the hedge fund space, as Executive Director for the Hedge Fund Business Operations Association. Victoria is a frequent contributor to ACM SIGGRAPH and is Immersive Chair for the SIGGRAPH 2019 Conference. She's also an active member of the Consumer Technology Association's AI Working Group.

 

Orr Danon

CEO
Hailo

Orr Danon is co-founder and CEO of Hailo Technologies. Prior to starting Hailo, Orr spent a decade as a group leader in a leading technological unit of the Israeli Defense Forces, where he led some of the largest and most complex interdisciplinary projects in the Israeli intelligence community. For this work, Orr received the Israel Defense Award from the President of Israel and the Creative Thinking Award from the Head of Military Intelligence. Orr earned a B.Sc. and physics and mathematics from the Hebrew University as part of the ”Talpiot” program and an M.Sc.

Orr Danon

CEO
Hailo

Orr Danon

CEO
Hailo

Orr Danon is co-founder and CEO of Hailo Technologies. Prior to starting Hailo, Orr spent a decade as a group leader in a leading technological unit of the Israeli Defense Forces, where he led some of the largest and most complex interdisciplinary projects in the Israeli intelligence community. For this work, Orr received the Israel Defense Award from the President of Israel and the Creative Thinking Award from the Head of Military Intelligence. Orr earned a B.Sc. and physics and mathematics from the Hebrew University as part of the ”Talpiot” program and an M.Sc. in electrical engineering (cum laude) from Tel Aviv University.

 

Mike Henry

Co-Founder & CEO
Mythic

Mike Henry

Co-Founder & CEO
Mythic

Mike Henry

Co-Founder & CEO
Mythic
 

Florian Netter

Tech Lead Compute Hardware and AI
Autonomous Intelligent Driving GmbH

Florian Netter

Tech Lead Compute Hardware and AI
Autonomous Intelligent Driving GmbH

Florian Netter

Tech Lead Compute Hardware and AI
Autonomous Intelligent Driving GmbH
 

Roland Angst

Head of ASUS Robotics & AI Centre
ASUS

Roland Angst is the Head of the ASUS Robotics and AI Center in Singapore an​d Senior Director of Articial Intelligence and Robotics at ASUS in Taipei. Since No​vember 2015 he has served as a lead software architect for ASUS Zenbo, an Android-based robot for the home, and as lead advisor for cross-functional robotics, computer vision, and machine learning teams.

Roland Angst

Head of ASUS Robotics & AI Centre
ASUS

Roland Angst

Head of ASUS Robotics & AI Centre
ASUS

Roland Angst is the Head of the ASUS Robotics and AI Center in Singapore an​d Senior Director of Articial Intelligence and Robotics at ASUS in Taipei. Since No​vember 2015 he has served as a lead software architect for ASUS Zenbo, an Android-based robot for the home, and as lead advisor for cross-functional robotics, computer vision, and machine learning teams. With the guidance of his technical expertise​, ASUS is creating an inspiring new line of products and services based on cutting-edge research and technologies.   Prior to joining ASUS, as a Junior Group Leader of the Vision, Geometry, and Computational Perception Group, Roland was affiliated with the Center for Visual Computing and Communication at the Max Planck Institute for Informatics. From February 2013 to March 2015, he was visiting assistant professor with the Image, Video, and Multimedia Systems and the Geometric Computation groups at Stanford University. ​As an active member of the global computer vision community, Roland frequently contributes both as an author and reviewer to journals and prestigious international conferences, including ICCV, CVPR, ECCV, Siggraph, IJCV and PAMI.   In 2012, ​Roland​ received his Ph.D in computer vision from ETH, the Swiss Federal Institute of Technology in Zürich. ​While working toward a doctorate, in 2010 he won ​a Google European Doctoral Fellowship in Computer Vision.​ In 2008, his master’s thesis has been awarded with an ETH medal and i​n 2007, he received his master's degree with distinction in computer science from ETH.

 

Robert Krutsch

Chief Architect
Zenuity

Krutsch Robert is the Chief Architect of Zenuity, a joint venture between Veoneer and Volvo Cars, that focuses on delivering ADAS and AD solutions. He holds more than 20 patents and is the author of various articles and books targeting signal and image processing. He received his Dipl. from “Politehnica” University Timisoara and University Bremen and is passionate about machine learning applications in computer vision and natural language processing.

Robert Krutsch

Chief Architect
Zenuity

Robert Krutsch

Chief Architect
Zenuity

Krutsch Robert is the Chief Architect of Zenuity, a joint venture between Veoneer and Volvo Cars, that focuses on delivering ADAS and AD solutions. He holds more than 20 patents and is the author of various articles and books targeting signal and image processing. He received his Dipl. from “Politehnica” University Timisoara and University Bremen and is passionate about machine learning applications in computer vision and natural language processing.

 

Matt Mattina

Head of Arm's Machine Learning Lab
Arm

Matthew Mattina is head of Arm’s Machine Learning Research Lab, where he leads a team of world-class ML researchers. The lab is focused on developing hardware, ML models, and optimization techniques to deliver energy efficient ML execution on Arm devices, from server to mobile to IoT. Prior to Arm, Matt was CTO at multicore chip company Tilera, and a processor architect at Intel and DEC. Matt has been granted over 40 patents relating to processor design, neural networks, and on-chip interconnects.

Matt Mattina

Head of Arm's Machine Learning Lab
Arm

Matt Mattina

Head of Arm's Machine Learning Lab
Arm

Matthew Mattina is head of Arm’s Machine Learning Research Lab, where he leads a team of world-class ML researchers. The lab is focused on developing hardware, ML models, and optimization techniques to deliver energy efficient ML execution on Arm devices, from server to mobile to IoT. Prior to Arm, Matt was CTO at multicore chip company Tilera, and a processor architect at Intel and DEC. Matt has been granted over 40 patents relating to processor design, neural networks, and on-chip interconnects. Matt holds an MS in Electrical Engineering from Princeton University, and a BS in Computer and Systems Engineering from Rensselaer Polytechnic Institute.

 

Albert Cohen

Research Scientist
Google

Albert Cohen is a research scientist at Google. He has been a research scientist at Inria from 2000 to 2018. He graduated from École Normale Supérieure de Lyon and received his PhD from the University of Versailles in 1999. He has been a visiting scholar at the University of Illinois, an invited professor at Philips and NXP Research, and a visiting scientist at Facebook Artificial Intelligence Research.

Albert Cohen

Research Scientist
Google

Albert Cohen

Research Scientist
Google

Albert Cohen is a research scientist at Google. He has been a research scientist at Inria from 2000 to 2018. He graduated from École Normale Supérieure de Lyon and received his PhD from the University of Versailles in 1999. He has been a visiting scholar at the University of Illinois, an invited professor at Philips and NXP Research, and a visiting scientist at Facebook Artificial Intelligence Research. Albert Cohen works on parallelizing and optimizing compilers, parallel programming and synchronous languages, with applications to high-performance computing, machine learning and reactive control systems. Several research projects led by Albert Cohen led to effective transfer to production compilers and programming environments.

 

Brett Simpson

Co-Founder & Partner
Arete Research

Brett Simpson is a co-founder of Arete (formed in 2000) and is based in the firm's London office. He focuses on the global semiconductor component sector. Brett is a regular public speaker at industry events and after 17 years looking at the sector, has a wealth of experience to draw on. Prior to Arete, Brett spent two years at Goldman Sachs in an equity analyst role, specialising in European technology following three years with Ericsson UK, working in business development, covering all aspects of wireline and wireless telecom infrastructure.

Brett Simpson

Co-Founder & Partner
Arete Research

Brett Simpson

Co-Founder & Partner
Arete Research

Brett Simpson is a co-founder of Arete (formed in 2000) and is based in the firm's London office. He focuses on the global semiconductor component sector. Brett is a regular public speaker at industry events and after 17 years looking at the sector, has a wealth of experience to draw on. Prior to Arete, Brett spent two years at Goldman Sachs in an equity analyst role, specialising in European technology following three years with Ericsson UK, working in business development, covering all aspects of wireline and wireless telecom infrastructure.

 

Eric Flamand

Co-Founder & CTO
GreenWaves Technologies

Eric got his PhD in Computer Science from INPG, France, in 1982. For the first part of his career he worked as a researcher with CNET and CNRS in France, on architectural automatic synthesis, design and architecture, compiler infrastructure for highly constrained heterogeneous small parallel processors. Eric then held different technical management in the semiconductor industry, first with Motorola where he was involved into the architecture definition and tooling of the StarCore DSP.

Eric Flamand

Co-Founder & CTO
GreenWaves Technologies

Eric Flamand

Co-Founder & CTO
GreenWaves Technologies

Eric got his PhD in Computer Science from INPG, France, in 1982. For the first part of his career he worked as a researcher with CNET and CNRS in France, on architectural automatic synthesis, design and architecture, compiler infrastructure for highly constrained heterogeneous small parallel processors. Eric then held different technical management in the semiconductor industry, first with Motorola where he was involved into the architecture definition and tooling of the StarCore DSP. Then with ST microelectronics, first, Eric was in charge of all the software development of the Nomadik Application Processor and then in charge of the P2012 corporate initiative aiming at the development of a many core device. He is now co-founder and CTO of Greenwaves Technologies a French based startup developing an IOT processor derived from Pulp. He is also acting as a part time research consultant for ETH-Z.

 

Márton Fehér

SVP, Hardware
AIMotive

Márton Fehér

SVP, Hardware
AIMotive

Márton Fehér

SVP, Hardware
AIMotive
 

Oliver Wick

Technology Scout
BMW

Oliver Wick

Technology Scout
BMW

Oliver Wick

Technology Scout
BMW
 

Omri Green

Partner
Grove Ventures

Omri has been leading sales and business activities globally in different companies focusing on utilities and different industry verticals.

Prior to joining Grove, Omri was leading APAC activities in Claroty (part of Team8 group) and was co-founder and Vice President of business development at ICS2 - a cyber security startup focusing on protecting power, oil, gas, and petrochemicals plants.

Omri Green

Partner
Grove Ventures

Omri Green

Partner
Grove Ventures

Omri has been leading sales and business activities globally in different companies focusing on utilities and different industry verticals.

Prior to joining Grove, Omri was leading APAC activities in Claroty (part of Team8 group) and was co-founder and Vice President of business development at ICS2 - a cyber security startup focusing on protecting power, oil, gas, and petrochemicals plants.

Omri has over a decade of experience as global sales and business executive in technology driven companies such as Dune Networks and Broadcom where he led innovative technology projects in power generation, communication and wireless technologies.

Omri was promoted to Investment Partner after a tenure as Grove’s Investment Principal and is now leveraging his engineering background and managerial experience to create value to Grove’s portfolio companies with their global business activities.

 

Peter Debacker

Principal Member of Technical Staff & R&D Team Leader
IMEC

Peter Debacker (male) received the M.Sc. (Hons.) degree in electrical engineering from the Katholieke Universiteit Leuven, Leuven, Belgium, in 2004. He worked with Philips as a system engineer and at Essensium as a System Architect before joining IMEC, Leuven, in 2011. He is currently Program Manager in the Semiconductor Technology and Systems division.

Peter Debacker

Principal Member of Technical Staff & R&D Team Leader
IMEC

Peter Debacker

Principal Member of Technical Staff & R&D Team Leader
IMEC

Peter Debacker (male) received the M.Sc. (Hons.) degree in electrical engineering from the Katholieke Universiteit Leuven, Leuven, Belgium, in 2004. He worked with Philips as a system engineer and at Essensium as a System Architect before joining IMEC, Leuven, in 2011. He is currently Program Manager in the Semiconductor Technology and Systems division. He leads a team that researches semiconductor technology, architecture and algorithms to create efficient AI hardware ranging from DNN accelerators, to in-memory compute and neuromorphic hardware.  Besides AI specific hardware, he works on power-performance-area (PPA) optimization of scaled CMOS technologies (for 3nm and beyond), emerging memories and beyond CMOS technologies. In his past he has worked on IMEC’s low-power digital chip and processor architectures and implementation in advanced technology nodes. His current research interests include AI, machine learning and neuromorphic computing, computer architectures, design methodologies, design-technology co-optimization, reliability, variability and low power design.

 

Stephan Schenk

Research Manager
BASF

Stephan Schenk

Research Manager
BASF

Stephan Schenk

Research Manager
BASF
 

Yulia Sandamirskaya

Group Leader
ETH Zurich

Yulia Sandamirskaya is a Group Leader at the Institute of Neuroinformatics (INI) of the University of Zurich and ETH Zurich. Her group “Neuromorphic Cognitive Robots” develops neuro-dynamic architectures for embodied AI. Her research interest is in memory formation, adaptive motor control, and autonomous learning in spiking and analogue neural networks. Her group works on implementing neuronal architectures in neuromorphic hardware to control robots. She has a degree in Physics from the Belarussian State University in Minsk, Belarus and Dr. rer. nat.

Yulia Sandamirskaya

Group Leader
ETH Zurich

Yulia Sandamirskaya

Group Leader
ETH Zurich

Yulia Sandamirskaya is a Group Leader at the Institute of Neuroinformatics (INI) of the University of Zurich and ETH Zurich. Her group “Neuromorphic Cognitive Robots” develops neuro-dynamic architectures for embodied AI. Her research interest is in memory formation, adaptive motor control, and autonomous learning in spiking and analogue neural networks. Her group works on implementing neuronal architectures in neuromorphic hardware to control robots. She has a degree in Physics from the Belarussian State University in Minsk, Belarus and Dr. rer. nat. from the Institute for Neural Computation in Bochum, Germany. She is the chair of EUCognition (the European Society for Cognitive Systems) and the coordinator of the NEUROTECH project that supports and develops the neuromorphic computing technology community in Europe.

AUDIENCE BREAKDOWN

AI Hardware Summit Audience Breakdown

Past attendees include: 

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